Conventionally, a synchronous DRAM (Dynamic Random Access Memory), that inputs and outputs data and a signal such as an address synchronously with a clock, is used in a wide range. While the speed of a clock used in a synchronous DRAM increases every year, the speed of a DRAM core cannot be increased in proportion to an input and output signal rate, because the DRAM core requires a precharge operation and a sense operation. Therefore, a synchronous DRAM has a “prefetch circuit” between a DRAM core and an input and output pin, and the prefetch circuit carries out a serial-parallel conversion, thereby achieving an apparent high-speed operation. See Patent Laid-Open Nos. 2004-164769, 2004-310989, 2004-133961, 2003-272382, and 2004-310918.
For example, when a DRAM core operates at 133 MHz, a prefetch circuit executes a prefetch of four bits, thereby obtaining a data transfer rate of 533 MHz to transfer the data to the outside. Furthermore, when the DRAM core operates at 200 MHz, the prefetch circuit executes a prefetch of 16 bits, thereby obtaining a data transfer rate of 3.2 GHz.
However, when the data transfer rate increases using the prefetch circuit, it also becomes necessary to use a high-speed tester to test the operation of the DRAM. In other words, in order to test the DRAM that operates at 3.2 GHz, it is necessary to use a tester that can input and output data at 3.2 GHz. Therefore, a conventional tester that does not have this capacity cannot be used as it is. Furthermore, because the operation test of a DRAM is carried out in a wafer state before dicing, a probe of a tester also becomes relatively large. Therefore, a parasitic capacitance of the tester becomes larger than that of wiring actually used, and the speed of the tester cannot be increased easily.
These problems occur not only in the DRAM but also synchronous semiconductor memory devices in general.